One of semiconductor devices used for an inverter control to drive a load such as a motor is a HVIC (high voltage integrated circuit). The HVIC controls a power device accommodated in an inverter for driving a load.
Conventionally, as shown in FIG. 55, a HVIC 107 is used for driving the inverter. The HVIC 107 includes a high potential reference gate driving circuit 103, a low potential reference gate driving circuit 104, level shift elements 105a, 105b and a control circuit 106. The high potential reference gate driving circuit 103 corresponds to a high potential reference circuit for driving an IGBT 102a on a high potential side in an inverter circuit 101. The inverter circuit 101 drives a motor 100. The low potential reference gate driving circuit 104 corresponds to a low potential reference circuit for driving an IGBT 102b on a low potential side in an inverter circuit 101. The level shift elements 105a, 105b and the control circuit 106 are arranged between the high potential reference gate driving circuit 103 and the low potential reference gate driving circuit 104. The HVIC 107 transmits a signal via the level shift elements 105a, 105b so that the HVIC 107 performs level shift of a reference voltage in the high potential reference circuit and the low potential reference circuit. It is required for the HVIC 107 to be made into one chip in order to minimize the dimensions of the inverter. The HVIC 107 shown in FIG. 55 is also made into one chip.
However, in the HVIC 107 having the high potential reference circuit and the low potential reference circuit made into one chip, interference of potential between the high potential reference circuit and the low potential reference circuit occurs, so that the circuit may malfunction. Accordingly, conventionally, element isolation is performed with using a PN contact isolation structure, a dielectric isolation structure or a trench isolation structure in a SOI (silicon on insulator) substrate (e.g., described in the patent document No. 1). However, it is necessary to set a potential in an output part of the high potential reference circuit for driving the IGBT 102a to be a virtual GND potential as a reference potential on a high voltage side. Thus, when a low potential (e.g., 0V) is switched to a high potential (e.g., 750V) in case of the level shift in any one of the above element isolation structures, a high voltage (e.g., larger than 1200V) is generated with a rapid rising edge speed such as several tens kV/μsec, and therefore, a large potential oscillation amplitude occurs. It is difficult to manage this high voltage surge (defined as a dv/dt surge since voltage increase is high with respect to the rising edge period) having the rapid rising edge without malfunction of the circuit.
[Patent Document No. 1] JP-A-2006-93229
In the above element isolation structures, the trench isolation structure having the SOI substrate provides the strongest resistance against noise, and therefore, the trench isolation structure provides the highest possibility among the element isolation structures. However, in the HVIC having the trench isolation structure with using the SOI substrate, the potential interferes through a support substrate when the dv/dt surge is applied so that displacement current for charging and discharging a parasitic capacitance formed by an insulation layer between the support substrate and a semiconductor layer (i.e., a SOI layer) is generated. Thus, the circuit malfunctions. FIG. 56 is a cross sectional view of the HVIC when the displacement current is generated. As shown in this drawing, for example, the displacement current is generated in a current path such that the displacement current flows from a portion providing the virtual GND potential of the high potential reference circuit portion HV formed in the semiconductor layer 111 to the support substrate 112 via the insulation layer 113, and then, the displacement current flows into the portion providing the GND potential of the low potential reference circuit portion LV via the insulation layer 113.
The above difficulty may be improved such that the thickness of the insulation layer is thickened so as to reduce the parasitic capacitance, or the impurity concentration on the support substrate 112 side is decreased so as to increase a resistance so that propagation of the displacement current is reduced. However, it is difficult to improve completely the difficulty since a tiny displacement current may cause the malfunction when an amplifier circuit having a large gain or the like is integrated.